In modern deep learning applications the data exchange among different integrated circuits may occur at rates up to tens of giga bit per second per data lane with an energy consumption in the range of pico-joules per bit. The channel loss at such a high frequency introduces inter-symbol interference (ISI) which limits the communication speed and requires more power for compensation. In this context, “inter-symbol interference” refers to a form of distortion of a signal in which one communicated symbol interferes with others.
To mitigate these effects various equalization schemes may be utilized such as signal transmitter pre-emphasis, multi-stage signal receiver continuous-time linear equalization (CTLE) and multi-tap signal receiver decision feedback equalization (DFE), resulting in design complexity and high power consumption.
A need therefore exists for a low power and low complexity signal transceiver design with significant equalization ability, larger peaking gain, higher peaking frequency, and less signal receiver noise than conventional approaches. The amplifier gain plot 100 of FIG. 1 depicts an example of peaking gain and peaking frequency.